Voltage generation circuit and display unit comprising voltage generation circuit

ABSTRACT

A voltage generation circuit including a capacitor, an n-channel MOS transistor, a p-channel MOS transistor and the like. The n-channel transistor has a source terminal connected to a node and a drain terminal employed as an output terminal for a negative voltage, the p-channel MOS transistor has a source terminal connected to the aforementioned node and a drain terminal employed as a ground terminal, gate terminals of the n-channel MOS transistor and the p-channel transistor are connected in common, and clock signals inverted in phase to each other are applied to the common node and a first terminal of the capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage generation circuit employinga capacitor and a display unit comprising this voltage generationcircuit.

2. Description of the Related Art

FIG. 41 illustrates an exemplary conventional voltage generation circuitemploying a capacitor. The voltage generation circuit shown in FIG. 41comprises a capacitor (pumping capacitor) cp1, first and secondp-channel MOS (metal oxide semiconductor) transistors pt1 and pt2, aninverter circuit inv1 and the like.

The first p-channel MOS transistor (driving transistor) pt1 has a drainterminal D and a gate terminal G connected to a node nd1 and a sourceterminal S defining a voltage output terminal 30 outputting a negativevoltage VBB. The second p-channel transistor pt2 has a source terminal Sconnected to the node nd1, a gate terminal G connected to the invertercircuit inv1, and a drain terminal D defining a ground terminal.

The capacitor cp1 is formed by a p-channel transistor having a sourceterminal and a drain terminal connected in common with each other and agate terminal G connected to the node nd1. A clock signal CLK is inputin the capacitor cp1 and the inverter circuit inv1 through an inputterminal 10.

The outline of operation of the voltage generation circuit having theaforementioned structure for generating the voltage (negative voltage)VBB is now described.

When the clock signal CLK goes low in logic (hereinafter simply referredto as “low”), the potential Vn1 of the node nd1 lowers to reach anegative voltage. When the potential Vn1 of the node nd1 lowers belowthe potential VBB of the source terminal S of the first p-channel MOStransistor pt1 in excess of the threshold voltage Vthp1 of the firstp-channel MOS transistor pt1, the first p-channel transistor pt1 isturned on.

At this time, charges proportional to the capacitance of the capacitorcp1 flow from the source terminal S of the first p-channel MOStransistor pt1 toward the node nd1. These charges are stored in thecapacitor cp1 since the second p-channel MOS transistor pt2 is in an OFFstate, and the potential Vn1 of the node nd1 rises in response to thesecharges.

When the clock signal CLK goes high in logic (hereinafter simplyreferred to as “high”), the potential Vn1 of the node nd1 is pulled upby a level corresponding to the high level (VDD) of the clock signalCLK, to further rise.

When the clock signal CLK goes high, further, a low-level signal isinput in the second p-channel MOS transistor pt2 through the invertercircuit inv1, to turn on the second p-channel MOS transistor pt2. Atthis time, the charges stored in the capacitor cp1 are extracted to theground terminal (GND), and the potential Vn1 of the node nd1 lowers.

Thus, the charges are pumped from the source terminal S of the firstp-channel MOS transistor pt1 to the ground terminal (GND) every cycle ofthe clock signal CLK, thereby rendering the voltage of the sourceterminal S of the first p-channel MOS transistor pt1 negative.

FIG. 42 shows a voltage generation circuit known as an example improvingthe pumping efficiency of the afore-mentioned conventional voltagegeneration circuit. This voltage generation circuit uses twoconventional voltage generation circuits described above, and appliesclock signals CLK and /CLK inverted in phase to each other to terminalsof pumping capacitors cp1 and cp2 respectively thereby improving thepumping efficiency thereof and reducing the time for attaining aprescribed negative voltage.

While the aforementioned conventional voltage generation circuiteffectively generates the voltage (negative voltage) VBB with a simplestructure, the theoretical value of the achieved negative voltage (VBB)is (−VDD+Vthp1+Vthp2) in FIG. 41 and (−VDD+Vthp1) in FIG. 42, which isless than the maximum logical value (−VDD) by the threshold voltage(Vthp1, Vthp2) of the first and second p-channel MOS transistors pt1 andpt2.

As the output negative voltage VBB lowers, further, the potentialdifference between the source terminal S of the first p-channel MOStransistor pt1 and the node nd1, i.e., the gate-to-source voltage of thefirst p-channel MOS transistor pt1 reduces to lower the drivability ofthe first p-channel MOS transistor pt1.

In recent years, a voltage generation circuit having high currentdrivability is required in view of current drivability necessary forcontrolling word lines of a DRAM (dynamic random access memory) with anegative bias or in view of reduction in power consumption andattainment of operating margins of pixel transistors in a liquid crystaldisplay unit or the like. However, the aforementioned conventionalvoltage generation circuit cannot sufficiently satisfy such requirementsdue to the low current drivability.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a voltage generationcircuit capable of obtaining a high voltage with high currentdrivability and a display unit comprising this voltage generator.

A voltage generation circuit according to an aspect of the presentinvention has a capacitor and generates a prescribed voltage through anode connected to a first terminal of the capacitor, and furthercomprises an n-channel transistor having one of a source terminal and adrain terminal connected to the node with the other one of the sourceterminal and the drain terminal defining an output terminal outputtingthe prescribed voltage and a p-channel transistor having one of a sourceterminal and a drain terminal connected to the node with the other oneof the source terminal and the drain terminal defining a referencepotential terminal, while gate terminals of the n-channel transistor andthe p-channel transistor are connected in common, one of two clocksignals inverted in phase to each other is applied to a second terminalof the capacitor, and the other one of the two clock signals is appliedto the gate terminals connected in common.

The voltage generation circuit can obtain an output voltage notinfluenced by the threshold voltage Vth of the n-channel transistorserving as a driving transistor. When generating a negative voltage, forexample, the driving transistor is reliably turned on also when theoutput negative voltage lowers, whereby the drivability of the drivingtransistor can be sufficiently secured regardless of the value of thenegative voltage. Further, the n-channel transistor is employed as thedriving transistor, whereby the operating speed of the voltagegeneration circuit can be increased as compared with the case ofemploying the p-channel transistor, and the drivability can beincreased. When securing ability equivalent to that of the p-channeltransistor with the n-channel transistor, further, the element areas ofthe transistors can be reduced.

The voltage generation circuit is preferably formed on a P-typesemiconductor substrate having a triple well structure, the n-channeltransistor preferably includes a MOSFET formed on a P-type well to whichthe output terminal is connected for obtaining its back gate potential,the p-channel transistor preferably includes a MOSFET formed on anN-type well to which a positive potential is applied for obtaining itsback gate potential, and the capacitor preferably includes an n-channeltransistor separately formed on a P-type well with a source terminal anda drain terminal connected in common and a gate terminal connected tothe node.

The voltage generation circuit may be formed on an N-type semiconductorsubstrate having a double well structure, the n-channel transistor mayinclude a MOSFET formed on a P-type well to which the output terminal isconnected for obtaining its back gate potential, the p-channeltransistor may include a MOSFET formed on an N-type well to which apositive potential is applied for obtaining its back gate potential, andthe capacitor may include an n-channel transistor separately formed on aP-type well with a source terminal and a drain terminal connected incommon and a gate terminal connected to the node.

The voltage generation circuit may be formed on a glass substrate, anactive layer of each of the n-channel transistor and the p-channeltransistor may be formed from a semiconductor layer formed on the glasssubstrate, and at least one electrode of the capacitor may be formedfrom an n-type region or a p-type region formed on part of thesemiconductor layer.

The voltage generation circuit preferably further comprises an invertercircuit for forming the two clock signals on the basis of a single clocksignal.

In this case, the two clock signals can be formed from the single clocksignal, whereby the structure of an external circuit can be simplifiedas compared with the case of employing the two clock signals from thefirst. Further, the voltage can be effectively generated due to a delayeffect through the inverter circuit.

The two clock signals preferably have a period when both of the twoclock signals go low in logic in phase inversion.

In this case, the two clock signals have the period when both of thesame go low in logic, whereby the potential of the node can be set to apositive voltage after reliably turning off the driving transistor, forexample, for effectively generating the negative voltage.

The voltage generation circuit may further comprise a logic circuit forforming the two clock signals on the basis of a single clock signal, anda delay circuit adjusting a period so that the two clock signals have aperiod when both of the two clock signals go low in logic in phaseinversion.

In this case, a pair of clock signals having the period when both of thetwo clock signals go low in logic in phase inversion can be readily andautomatically produced on the basis of the single clock signal.

A voltage generation circuit according to another aspect of the presentinvention has first and second capacitors and generates a prescribedvoltage through first and second nodes connected to first terminals ofthe first and second capacitors respectively, and further comprises afirst n-channel transistor having one of a source terminal and a drainterminal connected to the first node with the other one of the sourceterminal and the drain terminal defining an output terminal outputtingthe prescribed voltage, a second n-channel transistor having one of asource terminal and a drain terminal connected to the second node withthe other one of the source terminal and the drain terminal defining anoutput terminal outputting the prescribed voltage, a first p-channeltransistor having one of a source terminal and a drain terminalconnected to the first node with the other one of the source terminaland the drain terminal defining a reference potential terminal, and asecond p-channel transistor having one of a source terminal and a drainterminal connected to the second node with the other one of the sourceterminal and the drain terminal defining a reference potential terminal,while a gate terminal of the first n-channel transistor and a gateterminal of the first p-channel transistor are connected in common andconnected to the second node, a gate terminal of the second n-channeltransistor and the gate terminal of second p-channel transistor areconnected in common and connected to the first node, the outputterminals of the first and second n-channel transistors are connected incommon, one of two clock signals inverted in phase to each other isapplied to a second terminal of the first capacitor, and the other oneof the two clock signals is applied to a second terminal of the secondcapacitor.

The voltage generation circuit can obtain an output voltage notinfluenced by the threshold voltage Vth of the first and secondn-channel transistors serving as driving transistors. When generating anegative voltage, for example, the driving transistors are reliablyturned on also when the output negative voltage lowers, whereby thedrivability of the driving transistors can be sufficiently securedregardless of the value of the negative voltage. Further, the n-channeltransistors are employed as the driving transistors, whereby theoperating speed of the voltage generation circuit can be increased ascompared with the case of employing the p-channel transistors, and thedrivability can be increased. When securing ability equivalent to thatof the p-channel transistors with the n-channel transistors, further,the element areas of the transistors can be reduced.

In addition, pumping operation is performed every half cycle of theclock signals, whereby pumping can be more efficiently performed forincreasing the speed for reaching the target output voltage.

The voltage generation circuit is preferably f formed on a P-typesemiconductor substrate having a triple well structure, each of thefirst and second n-channel transistors preferably includes a MOSFETformed on a P-type well to which the output terminal is connected forobtaining its back gate potential, each of the first and secondp-channel transistors preferably includes a MOSFET formed on an N-typewell to which the clock signal is applied for obtaining its back gatepotential, the first capacitor preferably includes a p-channeltransistor separately formed on an N-type well with a source terminaland a drain terminal connected in common and a gate terminal connectedto the first node, and the second capacitor preferably includes ap-channel transistor separately formed on an N-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to the second node.

The voltage generation circuit may be formed on a P-type semiconductorsubstrate having a triple well structure, each of the first and secondn-channel transistors may include a MOSFET formed on a P-type well towhich the output terminal is connected for obtaining its back gatepotential, each of the first and second p-channel transistors mayinclude a MOSFET formed on an N-type well to which a positive potentialis applied for obtaining its back gate potential, the first capacitormay include a p-channel transistor separately formed on an N-type wellwith a source terminal and a drain terminal connected in common and agate terminal connected to the first node, and the second capacitor mayinclude a p-channel transistor separately formed on an N-type well witha source terminal and a drain terminal connected in common and a gateterminal connected to the second node.

The voltage generation circuit may be formed on a P-type semiconductorsubstrate having a triple well structure, each of the first and secondn-channel transistors may include a MOSFET formed on a P-type well towhich the output terminal is connected for obtaining its back gatepotential, each of the first and second p-channel transistors mayinclude a MOSFET formed on an N-type well to which a positive potentialis applied for obtaining its back gate potential, the first capacitormay include an n-channel transistor separately formed on a P-type wellwith a source terminal and a drain terminal connected in common and agate terminal connected to the first node, and the second capacitor mayinclude an n-channel transistor separately formed on a P-type well witha source terminal and a drain terminal connected in common and a gateterminal connected to the second node.

The voltage generation circuit may be formed on a P-type semiconductorsubstrate having a double well structure, each of the first and secondn-channel transistors may include a MOSFET formed on a P-type well towhich the output terminal is connected for obtaining its back gatepotential, each of the first and second p-channel transistors mayinclude a MOSFET formed on an N-type well to which a positive potentialis applied for obtaining its back gate potential, the first capacitormay include an n-channel transistor separately formed on a P-type wellwith a source terminal and a drain terminal connected in common and agate terminal connected to the first node, and the second capacitor mayinclude an n-channel transistor separately formed on a P-type well witha source terminal and a drain terminal connected in common and a gateterminal connected to the second node.

The voltage generation circuit may be formed on an insulator film formedon a silicon substrate, an active layer of each of the first and secondn-channel transistors and the first and second p-channel transistors maybe formed from a semiconductor layer formed on the insulator film, andat least one electrode of each of the first and second capacitors isformed from an n-type region or a p-type region formed on part of thesemiconductor layer.

The voltage generation circuit may be formed on a glass substrate, anactive layer of each of the first and second n-channel transistors andthe first and second p-channel transistors may be formed from asemiconductor layer formed on the glass substrate, and at least oneelectrode of each of the first and second capacitors may be formed froman n-type region or a p-type region formed on part of the semiconductorlayer.

The voltage generation circuit preferably further comprises an invertercircuit for forming the two clock signals on the basis of a single clocksignal.

In this case, the two clock signals can be formed from the single clocksignal, whereby the structure of an external circuit can be simplifiedas compared with the case of employing the two clock signals from thefirst. Further, the voltage can be effectively generated due to a delayeffect through the inverter circuit.

The two clock signals preferably have a period when both of the twoclock signals go low in logic in phase inversion.

In this case, the two clock signals have the period when both of the twoclock signals go low in logic, whereby the potential of the node can beset to a positive voltage after reliably turning off the drivingtransistors, for example, for effectively generating the negativevoltage.

The voltage generation circuit may further comprise a logic circuit forforming the two clock signals on the basis of a single clock signal anda delay circuit adjusting a period so that the two clock signals have aperiod when both of the two clock signals go low in logic in phaseinversion.

In this case, a pair of clock signals having the period when both of thetwo clock signals go low in logic in phase inversion can be readily andautomatically produced on the basis of the single clock signal.

A voltage generation circuit according to still another aspect of thepresent invention has a capacitor and generates a prescribed voltagethrough a node connected to a first terminal of the capacitor, andfurther comprises a first n-channel transistor having one of a sourceterminal and a drain terminal connected to the node with the other oneof the source terminal and the drain terminal defining an outputterminal outputting the prescribed voltage and a second n-channeltransistor having one of a source terminal and a drain terminal as wellas a gate terminal connected to the node with the other one of thesource terminal and the drain terminal defining a reference potentialterminal, while one of two clock signals inverted in phase to each otheris applied to a second terminal of the capacitor and the other one ofthe two clock signals is applied to a gate terminal of the firstn-channel transistor.

The voltage generation circuit can obtain an output voltage notinfluenced by the threshold voltage Vth of the first n-channeltransistor serving as a driving transistor. When generating a negativevoltage, for example, the driving transistor is reliably turned on alsowhen the output negative voltage lowers, whereby the drivability of thedriving transistor can be sufficiently secured regardless of the valueof the negative voltage. Further, the n-channel transistor is employedas the driving transistor, whereby the operating speed of the voltagegeneration circuit can be increased as compared with the case ofemploying the p-channel transistor, and the drivability can beincreased. When securing ability equivalent to that of the p-channeltransistor with the n-channel transistor, further, the element areas ofthe transistors can be reduced.

The voltage generation circuit is preferably formed on a P-typesemiconductor substrate having a triple well structure, the firstn-channel transistor preferably includes a MOSFET formed on a P-typewell to which the output terminal is connected for obtaining its backgate potential, the second n-channel transistor preferably includes aMOSFET formed on a P-type well to which the node is connected forobtaining its back gate potential, and the capacitor preferably includesan n-channel transistor separately formed on a P-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to the node.

The voltage generation circuit may be formed on an N-type semiconductorsubstrate having a double well structure, the first n-channel transistormay include a MOSFET formed on a P-type well to which the outputterminal is connected for obtaining its back gate potential, the secondn-channel transistor may include a MOSFET formed on a P-type well towhich the node is connected for obtaining its back gate potential, andthe capacitor may include an n-channel transistor separately formed on aP-type well with a source terminal and a drain terminal connected incommon and a gate terminal connected to the node.

The voltage generation circuit is preferably formed on a glasssubstrate, an active layer of each of the first and second n-channeltransistors is preferably formed from a semiconductor layer formed onthe glass substrate, and at least one electrode of the capacitor ispreferably formed from an n-type region formed on part of thesemiconductor layer.

The voltage generation circuit preferably further comprises an invertercircuit for forming the two clock signals on the basis of a single clocksignal.

In this case, the two clock signals can be formed from the single clocksignal, whereby the structure of an external circuit can be simplifiedas compared with the case of employing the two clock signals from thefirst. Further, the voltage can be effectively generated due to a delayeffect through the inverter circuit.

The two clock signals preferably have a period when both of the twoclock signals go low in logic in phase inversion.

In this case, the two clock signals have the period when both of the twoclock signals go low in logic, whereby the potential of the node can beset to a positive voltage after reliably turning off the drivingtransistors, for example, for effectively generating the negativevoltage.

The voltage generation circuit may further comprise a logic circuit forforming the two clock signals on the basis of a single clock signal anda delay circuit adjusting a period so that the two clock signals have aperiod when both of the two clock signals go low in logic in phaseinversion.

In this case, a pair of clock signals having the period when both of thetwo clock signals go low in logic in phase inversion can be readily andautomatically produced on the basis of the single clock signal.

A voltage generation circuit according to a further aspect of thepresent invention has first and second capacitors and generates aprescribed voltage through first and second nodes connected to firstterminals of the first and second capacitors respectively, and furthercomprises a first n-channel transistor having one of a source terminaland a drain terminal connected to the first node with the other one ofthe source terminal and the drain terminal defining an output terminaloutputting the prescribed voltage, a second n-channel transistor havingone of a source terminal and a drain terminal connected to the secondnode with the other one of the source terminal and the drain terminaldefining an output terminal outputting the prescribed voltage, a thirdn-channel transistor having one of a source terminal and a drainterminal as well as a gate terminal connected to the first node with theother one of the source terminal and the drain terminal defining areference potential terminal, and a fourth n-channel transistor havingone of a source terminal and a drain terminal as well as a gate terminalconnected to the second node with the other one of the source terminaland the drain terminal defining a reference potential terminal, whilethe output terminals of the first and second n-channel transistors areconnected in common, a gate terminal of the first n-channel transistoris connected to the second node, a gate terminal of the second n-channeltransistor is connected to the first node, one of two clock signalsinverted in phase to each other is applied to a second terminal of thefirst capacitor, and the other one of the two clock signals is appliedto a second terminal of the second capacitor.

The voltage generation circuit can obtain an output voltage notinfluenced by the threshold voltage Vth of the first and secondn-channel transistors serving as driving transistors. When generating anegative voltage, for example, the driving transistors are reliablyturned on also when the output negative voltage lowers, whereby thedrivability of the driving transistors can be sufficiently securedregardless of the value of the negative voltage. Further, the n-channeltransistors are employed as the driving transistors, whereby theoperating speed of the voltage generation circuit can be increased ascompared with the case of employing the p-channel transistors, and thedrivability can be increased. When securing ability equivalent to thatof the p-channel transistors with the n-channel transistors, further,the element areas of the transistors can be reduced.

In addition, pumping operation is performed every half cycle of theclock signals, whereby pumping can be more efficiently performed forincreasing the speed for reaching the target output voltage.

The voltage generation circuit is preferably formed on a P-typesemiconductor substrate having a triple well structure, each of thefirst and second n-channel transistors preferably includes a MOSFETformed on a P-type well to which the output terminal is connected forobtaining its back gate potential, the third n-channel transistorpreferably includes a MOSFET formed on a P-type well to which the firstnode is connected for obtaining its back gate potential, the fourthn-channel transistor preferably includes a MOSFET formed on a P-typewell to which the second node is connected for obtaining its back gatepotential, the first capacitor preferably includes an n-channeltransistor separately formed on a P-type well with a source terminal anda drain terminal connected in common and a gate terminal connected tothe first node, and the second capacitor preferably includes ann-channel transistor separately formed on a P-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to the second node.

The voltage generation circuit may be formed on a P-type semiconductorsubstrate having a double well structure, each of the first and secondn-channel transistors may include a MOSFET formed on a P-type well towhich the output terminal is connected for obtaining its back gatepotential, the third n-channel transistor may include a MOSFET formed ona P-type well to which the first node is connected for obtaining itsback gate potential, the fourth n-channel transistor may include aMOSFET formed on a P-type well to which the second node is connected forobtaining its back gate potential, the first capacitor may include ann-channel transistor separately formed on a P-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to the first node, and the second capacitor may include ann-channel transistor separately formed on a P-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to the second node.

The voltage generation circuit may be formed on a glass substrate, anactive layer of each of the first to fourth n-channel transistors may beformed from a semiconductor layer formed on the glass substrate, and atleast one electrode of each of the first and second capacitors may beformed from an n-type region formed on part of the semiconductor layer.

The voltage generation circuit preferably further comprises an invertercircuit for forming the two clock signals on the basis of a single clocksignal.

In this case, the two clock signals can be formed from the single clocksignal, whereby the structure of an external circuit can be simplifiedas compared with the case of employing the two clock signals from thefirst. Further, the voltage can be effectively generated due to a delayeffect through the inverter circuit.

The two clock signals preferably have a period when both of the twoclock signals go low in logic in phase inversion.

In this case, the two clock signals have the period when both of the twoclock signals go low in logic, whereby the potential of the node can beset to a positive voltage after reliably turning off the drivingtransistors, for example, for effectively generating the negativevoltage.

The voltage generation circuit may further comprise a logic circuit forforming the two clock signals on the basis of a single clock signal anda delay circuit adjusting a period so that said two clock signals have aperiod when both of the two clock signals go low in logic in phaseinversion.

In this case, a pair of clock signals having the period when both of thetwo clock signals go low in logic in phase inversion can be readily andautomatically produced on the basis of the single clock signal.

A display unit according to a further aspect of the present inventioncomprises a plurality of display pixels arranged on intersectionsbetween a plurality of scan lines and a plurality of data lines in theform of a matrix, a plurality of active switching elements provided forthe respective display pixels for controlling a voltage applied to thedisplay pixels, a scan line driving circuit scanning the plurality ofscan lines while applying a driving voltage for activating the pluralityof active switching elements and a voltage generation circuit outputtinga prescribed voltage to the scan line driving circuit, while the voltagegeneration circuit has a capacitor and generates the prescribed voltagethrough a node connected to a first terminal of the capacitor, thevoltage generation circuit further includes an n-channel transistorhaving one of a source terminal and a drain terminal connected to thenode with the other one of the source terminal and the drain terminaldefining an output terminal outputting the prescribed voltage and ap-channel transistor having one of a source terminal and a drainterminal connected to the node with the other one of the source terminaland the drain terminal defining a reference potential terminal, gateterminals of the n-channel transistor and the p-channel transistor areconnected in common, one of two clock signals inverted in phase to eachother is applied to a second terminal of the capacitor, and the otherone of the two clock signals is applied to the gate terminals connectedin common.

When the voltage generation circuit generates a negative voltage in thedisplay unit, power consumption can be reduced and operating margins ofthe active switching elements can be increased by employing a voltagefrom a prescribed negative voltage to half a power supply voltage, forexample, as a voltage applied to the scan lines. Further, thecapacitance of an external capacitor generally provided outside thedisplay unit as an element for storing negative charges can be soreduced that this capacitor can be miniaturized or omitted.

When the display unit is a liquid crystal display unit generallyrequired to reach a negative voltage as soon as possible upon powersupply, the aforementioned voltage generation circuit can quickly supplythe negative voltage due to its effective pumping operation. WhenAC-driving liquid crystal electrodes opposed to each other for reducingpower consumption, the gate potential of pixel transistors can be set toa lower negative potential due to the large achieved negative voltageregardless of the threshold voltage of transistors, whereby theaforementioned voltage generation circuit can prevent data leak andreduce power consumption. Further, the display quality of the liquidcrystal display unit can be improved by loading the voltage generationcircuit having a large driving current (drivability) on the liquidcrystal display unit.

The voltage generation circuit is preferably formed on a glasssubstrate, an active layer of each of the n-channel transistor and thep-channel transistor is preferably formed from a semiconductor layerformed on the glass substrate, and at least one electrode of thecapacitor is preferably formed from an n-type region or a p-type regionformed on part of the semiconductor layer.

The display unit preferably further comprises a level conversion circuitstepping up/converting the levels of signals applied to the voltagegeneration circuit as the clock signals. In this case, the voltagegeneration circuit can properly generate a voltage such as a prescribednegative voltage, for example, required by the display unit with theaforementioned level conversion circuit.

A display unit according to a further aspect of the present inventioncomprises a plurality of display pixels arranged on intersectionsbetween a plurality of scan lines and a plurality of data lines in theform of a matrix, a plurality of active switching elements provided forthe respective display pixels for controlling a voltage applied to thedisplay pixels, a scan line driving circuit scanning the plurality ofscan lines while applying a driving voltage for activating the pluralityof active switching elements and a voltage generation circuit outputtinga prescribed voltage to the scan line driving circuit, while the voltagegeneration circuit has first and second capacitors and generates theprescribed voltage through first and second nodes connected to firstterminals of the first and second capacitors respectively, the voltagegeneration circuit further includes a first n-channel transistor havingone of a source terminal and a drain terminal connected to the firstnode with the other one of the source terminal and the drain terminaldefining an output terminal outputting the prescribed voltage, a secondn-channel transistor having one of a source terminal and a drainterminal connected to the second node with the other one of the sourceterminal and the drain terminal defining an output terminal outputtingthe prescribed voltage, a first p-channel transistor having one of asource terminal and a drain terminal connected to the first node withthe other one of the source terminal and the drain terminal defining areference potential terminal and a second p-channel transistor havingone of a source terminal and a drain terminal connected to the secondnode with the other one of the source terminal and the drain terminaldefining a reference potential terminal, a gate terminal of the firstn-channel transistor and a gate terminal of the first p-channeltransistor are connected in common and connected to the second node, agate terminal of the second n-channel transistor and a gate terminal ofthe second p-channel transistor are connected in common and connected tothe first node, the output terminals of the first and second n-channeltransistors are connected in common, one of two clock signals invertedin phase to each other is applied to a second terminal of the firstcapacitor, and the other one of the two clock signals is applied to asecond terminal of the second capacitor.

When the voltage generation circuit generates a negative voltage in thedisplay unit, power consumption can be reduced and operating margins ofthe active switching elements can be increased by employing a voltagefrom a prescribed negative voltage to half a power supply voltage, forexample, as a voltage applied to the scan lines. Further, thecapacitance of an external capacitor generally provided outside thedisplay unit as an element for storing negative charges can be soreduced that this capacitor can be miniaturized or omitted.

When the display unit is a liquid crystal display unit generallyrequired to reach a negative voltage as soon as possible upon powersupply, the aforementioned voltage generation circuit can quickly supplythe negative voltage due to its effective pumping operation. WhenAC-driving liquid crystal electrodes opposed to each other for reducingpower consumption, the gate potential of pixel transistors can be set toa lower negative potential due to the large achieved negative voltageregardless of the threshold voltage of transistors, whereby theaforementioned voltage generation circuit can prevent data leak andreduce power consumption. Further, the display quality of the liquidcrystal display unit can be improved by loading the voltage generationcircuit having a large driving current (drivability) on the liquidcrystal display unit.

The voltage generation circuit is preferably formed on a glasssubstrate, an active layer of each of the first and second n-channeltransistors and the first and second p-channel transistors is preferablyformed from a semiconductor layer formed on the glass substrate, and atleast one electrode of each of the first and second capacitors is formedfrom an n-type region or a p-type region formed on part of thesemiconductor layer.

The display unit preferably further comprises a level conversion circuitstepping up/converting the levels of signals applied to the voltagegeneration circuit as the clock signals. In this case, the voltagegeneration circuit can properly generate a voltage such as a prescribednegative voltage, for example, required by the display unit with theaforementioned level conversion circuit.

A display unit according to a further aspect of the present inventioncomprises a plurality of display pixels arranged on intersectionsbetween a plurality of scan lines and a plurality of data lines in theform of a matrix, a plurality of active switching elements provided forthe respective display pixels for controlling a voltage applied to thedisplay pixels, a scan line driving circuit scanning the plurality ofscan lines while applying a driving voltage for activating the pluralityof active switching elements and a voltage generation circuit outputtinga prescribed voltage to the scan line driving circuit, while the voltagegeneration circuit has a capacitor and generates a prescribed voltagethrough a node connected to a first terminal of the capacitor, thevoltage generation circuit further includes a first n-channel transistorhaving one of a source terminal and a drain terminal connected to thenode with the other one of the source terminal and the drain terminaldefining an output terminal outputting the prescribed voltage and asecond n-channel transistor having one of a source terminal and a drainterminal as well as a gate terminal connected to the node with the otherone of the source terminal and the drain terminal defining a referencepotential terminal, one of two clock signals inverted in phase to eachother is applied to a second terminal of the capacitor, and the otherone of the two clock signals is applied to a gate terminal of the firstn-channel transistor.

When the voltage generation circuit generates a negative voltage in thedisplay unit, power consumption can be reduced and operating margins ofthe active switching elements can be increased by employing a voltagefrom a prescribed negative voltage to half a power supply voltage, forexample, as a voltage applied to the scan lines. Further, thecapacitance of an external capacitor generally provided outside thedisplay unit as an element for storing negative charges can be soreduced that this capacitor can be miniaturized or omitted.

When the display unit is a liquid crystal display unit generallyrequired to reach a negative voltage as soon as possible upon powersupply, the aforementioned voltage generation circuit can quickly supplythe negative voltage due to its effective pumping operation. WhenAC-driving liquid crystal electrodes opposed to each other for reducingpower consumption, the gate potential of pixel transistors can be set toa lower negative potential due to the large achieved negative voltageregardless of the threshold voltage of transistors, whereby theaforementioned voltage generation circuit can prevent data leak andreduce power consumption. Further, the display quality of the liquidcrystal display unit can be improved by loading the voltage generationcircuit having a large driving current (drivability) on the liquidcrystal display unit.

The voltage generation circuit is preferably formed on a glasssubstrate, an active layer of each of the first and second n-channeltransistors is preferably formed from a semiconductor layer formed onthe glass substrate, and at least one electrode of the capacitor ispreferably formed from an n-type region formed on part of thesemiconductor layer.

The display unit preferably further comprises a level conversion circuitstepping up/converting the levels of signals applied to the voltagegeneration circuit as the clock signals. In this case, the voltagegeneration circuit can properly generate a voltage such as a prescribednegative voltage, for example, required by the display unit with theaforementioned level conversion circuit.

A display unit according to a further aspect of the present inventioncomprises a plurality of display pixels arranged on intersectionsbetween a plurality of scan lines and a plurality of data lines in theform of a matrix, a plurality of active switching elements provided forthe respective display pixels for controlling a voltage applied to thedisplay pixels, a scan line driving circuit scanning the plurality ofscan lines while applying a driving voltage for activating the pluralityof active switching elements and a voltage generation circuit outputtinga prescribed voltage to the scan line driving circuit, while the voltagegeneration circuit has first and second capacitors and generates theprescribed voltage through first and second nodes connected to firstterminals of the first and second capacitors respectively, the voltagegeneration circuit further includes a first n-channel transistor havingone of a source terminal and a drain terminal connected to the firstnode with the other one of the source terminal and the drain terminaldefining an output terminal outputting the prescribed voltage, a secondn-channel transistor having one of a source terminal and a drainterminal connected to the second node with the other one of the sourceterminal and the drain terminal defining an output terminal outputtingthe prescribed voltage, a third n-channel transistor having one of asource terminal and a drain terminal as well as a gate terminalconnected to the first node with the other one of the source terminaland the drain terminal defining a reference potential, and a fourthn-channel transistor having one of a source terminal and a drainterminal as well as a gate terminal connected to the second node withthe other one of the source terminal and the drain terminal defining areference potential terminal, the output terminals of the first andsecond n-channel transistors are connected in common, a gate terminal ofthe first n-channel transistor is connected to the second node, a gateterminal of the second n-channel transistor is connected to the firstnode, one of two clock signals inverted in phase to each other isapplied to a second terminal of the first capacitor, and the other oneof the two clock signals is applied to a second terminal of the secondcapacitor.

When the voltage generation circuit generates a negative voltage in thedisplay unit, power consumption can be reduced and operating margins ofthe active switching elements can be increased by employing a voltagefrom a prescribed negative voltage to half a power supply voltage, forexample, as a voltage applied to the scan lines. Further, thecapacitance of an external capacitor generally provided outside thedisplay unit as an element for storing negative charges can be soreduced that this capacitor can be miniaturized or omitted.

When the display unit is a liquid crystal display unit generallyrequired to reach a negative voltage as soon as possible upon powersupply, the aforementioned voltage generation circuit can quickly supplythe negative voltage due to its effective pumping operation. WhenAC-driving liquid crystal electrodes opposed to each other for reducingpower consumption, the gate potential of pixel transistors can be set toa lower negative potential due to the large achieved negative voltageregardless of the threshold voltage of transistors, whereby theaforementioned voltage generation circuit can prevent data leak andreduce power consumption. Further, the display quality of the liquidcrystal display unit can be improved by loading the voltage generationcircuit having a large driving current (drivability) on the liquidcrystal display unit.

The voltage generation circuit is preferably formed on a glasssubstrate, an active layer of each of the first to fourth n-channeltransistors is preferably formed from a semiconductor layer formed onthe glass substrate, and at least one electrode of each of the first andsecond capacitors is formed from an n-type region formed on part of thesemiconductor layer.

The display unit preferably further comprises a level conversion circuitstepping up/converting the levels of signals applied to the voltagegeneration circuit as the clock signals. In this case, the voltagegeneration circuit can properly generate a voltage, such as a prescribednegative voltage, for example, required by the display unit with theaforementioned level conversion circuit.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the basic circuit structure of avoltage generation circuit according to a first operation of the presentinvention;

FIG. 2 is a timing chart for illustrating operation of the voltagegeneration circuit shown in FIG. 1;

FIG. 3 is a sectional view showing an exemplary structure of the voltagegeneration circuit shown in FIG. 1 formed on a triple well structure;

FIG. 4 is a circuit diagram showing an equivalent circuit of the voltagegeneration circuit corresponding to the exemplary structure shown inFIG. 3;

FIG. 5 is a sectional view showing an exemplary structure of the voltagegeneration circuit shown in FIG. 1 formed on a double well structure;

FIG. 6 is a sectional view showing an exemplary structure of the voltagegeneration circuit shown in FIG. 1 formed on a glass substrate;

FIG. 7 is a circuit diagram showing the basic circuit structure of avoltage generation circuit according to a second embodiment of thepresent invention;

FIG. 8 is a circuit diagram showing a modification of the voltagegeneration circuit shown in FIG. 7;

FIG. 9 is a circuit diagram showing the basic circuit structure of avoltage generation circuit according to a third embodiment of thepresent invention;

FIG. 10 is a timing chart for illustrating operation of the voltagegeneration circuit shown in FIG. 9;

FIG. 11 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 9 formed on a triple wellstructure;

FIG. 12 is a circuit diagram showing an equivalent circuit of thevoltage generation circuit corresponding to the exemplary structureshown in FIG. 11;

FIG. 13 is a graph showing electric characteristics of the voltagegeneration circuit shown in FIG. 11 and a conventional voltagegeneration circuit in comparison with each other;

FIG. 14 is a graph showing other electric characteristics of the voltagegeneration circuit shown in FIG. 11 and the conventional voltagegeneration circuit in comparison with each other;

FIG. 15 is a graph showing further electric characteristics of thevoltage generation circuit shown in FIG. 11 and the conventional voltagegeneration circuit in comparison with each other;

FIG. 16 is a sectional view showing an exemplary structure of amodification of the voltage generation circuit shown in FIG. 9 formed ona triple well structure;

FIG. 17 is a circuit diagram showing an equivalent circuit of thevoltage generation circuit corresponding to the exemplary structureshown in FIG. 16;

FIG. 18 is a sectional view showing an exemplary structure of anothermodification of the voltage generation circuit shown in FIG. 9 formed ona triple well structure;

FIG. 19 is a circuit diagram showing an equivalent circuit of thevoltage generation circuit corresponding to the exemplary structureshown in FIG. 18;

FIG. 20 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 9 formed on a double wellstructure;

FIG. 21 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 9 formed on an insulator filmprovided on a silicon substrate;

FIG. 22 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 9 formed on a glass substrate;

FIG. 23 is a graph showing electric characteristics of the voltagegeneration circuit shown in FIG. 22 and a conventional voltagegeneration circuit in comparison with each other;

FIG. 24 is a graph showing other electric characteristics of the voltagegeneration circuit shown in FIG. 22 and the conventional voltagegeneration circuit in comparison with each other;

FIG. 25 is a sectional view showing another exemplary structure of thevoltage generation circuit shown in FIG. 9 formed on a glass substrate;

FIG. 26 is a timing chart showing modifications of clock signals appliedto the voltage generation circuit shown in FIG. 9;

FIG. 27 is a circuit diagram showing the structure of an exemplarycircuit automatically producing the clock signals shown in FIG. 26;

FIG. 28 is a circuit diagram showing the basic circuit structure of avoltage generation circuit according to a fourth embodiment of thepresent invention;

FIG. 29 is a timing chart for illustrating operation of the voltagegeneration circuit shown in FIG. 28;

FIG. 30 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 28 formed on a triple wellstructure;

FIG. 31 is a circuit diagram showing the structure of an equivalentcircuit of the voltage generation circuit corresponding to the exemplarystructure shown in FIG. 30;

FIG. 32 is a sectional view showing an exemplary structure of amodification of the voltage generation circuit shown in FIG. 28 formedon a double well structure;

FIG. 33 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 28 formed on a glass substrate;

FIG. 34 is a circuit diagram showing the basic circuit structure of avoltage generation circuit according to a fifth embodiment of thepresent invention;

FIG. 35 is a timing chart for illustrating operation of the voltagegeneration circuit shown in FIG. 34;

FIG. 36 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 34 formed on a triple wellstructure;

FIG. 37 is a circuit diagram showing an equivalent circuit of thevoltage generation circuit corresponding to the exemplary structureshown in FIG. 36;

FIG. 38 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 34 formed on a double wellstructure;

FIG. 39 is a sectional view showing an exemplary structure of thevoltage generation circuit shown in FIG. 34 formed on a glass substrate;

FIG. 40 is a block diagram schematically showing the structure of anembodiment of a display unit comprising the voltage generation circuitaccording to the present invention;

FIG. 41 is a circuit diagram showing the basic circuit structure of aconventional voltage generation circuit; and

FIG. 42 is a circuit diagram showing the basic circuit structure ofanother conventional voltage generation circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(First Embodiment)

A voltage generation circuit according to a first embodiment of thepresent invention is now described with reference to FIGS. 1 to 4.First, the basic structure of the voltage generation circuit accordingto the first embodiment of the present invention is described withreference to FIG. 1.

The voltage generation circuit shown in FIG. 1 comprises a capacitor(pumping capacitor) CP1, an n-channel MOS transistor NT1, a p-channelMOS transistor PT1 and the like.

The n-channel MOS transistor (driving transistor) NT1 has a sourceterminal S connected to a node ND1 and a drain terminal D defining avoltage output terminal 3 outputting a negative voltage VBB. Thep-channel MOS transistor PT1 has a source terminal S connected to thenode ND1 and a drain terminal D defining a ground terminal (referencepotential terminal). Gate terminals G of the n-channel MOS transistorNT1 and the p-channel MOS transistor PT1 are connected in common, andthe common node therebetween is connected to a clock input terminal 2.

The capacitor CP1 has a first electrode connected to the node ND1 and asecond electrode connected to a clock input terminal 1. Clock signalsCLK and /CLK (“/” denotes logic inversion) inverted in phase to eachother are applied to the clock input terminals 1 and 2 respectively. Thecapacitor CP1 may be formed by an n-channel MOS transistor or ap-channel MOS transistor having a source terminal and a drain terminalconnected in common.

The outline of operation for generating the voltage (negative voltage)from the voltage generation circuit having the aforementioned structureis now described with reference to FIG. 2. The clock signals CLK and/CLK shown at (a) and (b) in FIG. 2 are merely inverted in phase to eachother.

When the clock signal CLK starts to go low (0 V) at a time t1 shown inFIG. 2, the potential VN1 of the node ND1 lowers to reach a negativevoltage (see (a) and (c) in FIG. 2). When the clock signal /CLK goeshigh (VDD) at this time, the n-channel MOS transistor NT1 is turned on,and charges proportional to the capacitance of the capacitor CP1 flowfrom the drain terminal D of the transistor NT1 toward the node ND1.These charges are stored in the capacitor CP1 since the p-channel MOStransistor PT1 is in an OFF state, and the potential VN1 of the node ND1rises in response thereto (see (c) in FIG. 2).

Then, the clock signal CLK starts to go high at a time t2, whereby thepotential VN1 of the node ND1 is pulled up by a level corresponding tothe high level (VDD) of the clock signal CLK, and further rises. Whenthe clock signal CLK goes high, the clock signal /CLK goes low to turnon the p-channel MOS transistor PT1. Therefore, the charges stored inthe capacitor CP1 are extracted to the ground terminal (GND), followedby reduction of the potential VN1 of the node ND1 (see (c) in FIG. 2).

The clock signal CLK starts to go low again at a time t3, wherebyoperation similar to that at the aforementioned time t1 is performed.The aforementioned operation is so repeated as to pump the charges fromthe drain terminal D of the n-channel MOS transistor NT1 to the groundterminal every cycle of the clock signals CLK and /CLK, for renderingthe voltage VBB of the drain terminal D of the n-channel MOS transistorNT1 negative (see (d) in FIG. 2).

The theoretical value of the negative voltage VBB in the aforementionedvoltage generation circuit reaches (Vthp1-VDD).

Also when the output negative voltage VBB lowers, the potentialdifference between the source terminal S and the gate terminal G forturning on the n-channel MOS transistor NT1 is supplied by the clocksignal /CLK and hence drivability of the n-channel MOS transistor NT1can be sufficiently guaranteed regardless of the value of the negativevoltage VBB.

Further, the n-channel transistor NT1 is employed as the drivingtransistor, whereby the operating speed can be increased as comparedwith the case of employing the p-channel transistor as the drivingtransistor due to its characteristics, and the drivability can beimproved. When securing ability equivalent to that of the p-channeltransistor with the n-channel transistor, the element areas of thetransistors can be reduced.

The outline of the sectional structure of the voltage generation circuitaccording to this embodiment formed on a semiconductor substrate is nowdescribed with reference to FIG. 3. FIG. 4 shows an equivalent circuitof this case.

As shown in FIG. 3, the voltage generation circuit is formed on a P-typesilicon substrate having a triple well structure of P-type wells, anN-type well and still another P-type well (P-wells, an N-well and stillanother P-well).

The n-channel MOS transistor NT1 is formed on the P-type well as aMOSFET (field-effect transistor), and the drain terminal D (voltageoutput terminal) is connected to this P-type well for obtaining its backgate potential.

The p-channel MOS transistor PT1 is formed on the N-type well as aMOSFET, and a positive potential (VDD) is applied to this N-type wellfor obtaining its back gate potential.

The capacitor CP1 is separately formed on the other P-type well as ann-channel MOSFET having a source terminal and a drain terminal connectedin common, and its gate terminal G is connected to the node ND1.

According to the voltage generation circuit of the first embodiment, ashereinabove described, the following effects can be attained:

(1) When the output negative voltage VBB lowers, the n-channel MOStransistor NT1 is reliably turned on and hence the drivability of then-channel MOS transistor NT1 can be sufficiently guaranteed regardlessof the value of the output negative voltage VBB.

(2) The n-channel transistor is employed as the driving transistor,whereby the operating speed can be increased as compared with the caseof employing the p-channel transistor as the driving transistor, and thedrivability thereof can be improved. When securing ability equivalent tothat of the p-channel transistor with the n-channel transistor, theelement areas of the transistors can be reduced.

The aforementioned first embodiment can also be carried out in thefollowing modes:

(1) While the voltage generation circuit is formed on the P-type siliconsubstrate having a triple well structure in the first embodiment, thepresent invention is not particularly restricted to this. Theaforementioned voltage generation circuit may alternatively be formed onan N-type silicon substrate having a double well structure of an N-typewell and P-type wells as shown in FIG. 5, for example.

(2) The aforementioned voltage generation circuit may alternatively beformed on a glass substrate, as shown in FIG. 6. In this case, eachactive layer (source/drain region) of the n-channel MOS transistor NT1and the p-channel MOS transistor PT1 is formed from a semiconductorlayer of polycrystalline silicon or amorphous silicon located in aninterlayer isolation film 101 provided on the glass substrate. The gateelectrode G of each of the transistors NT1 and PT1 is formed by a thinfilm of metal chromium (Cr), for example. Alternatively, the gateelectrode G may be formed by a silicide thin film.

The capacitor CP1 is also formed on the aforementioned glass substrate,at least one electrode (a lower electrode 103 in FIG. 6) thereof isformed by an n-type region or a p-type region (the n-type region in FIG.6) formed on part of the aforementioned semiconductor layer, and anupper electrode 104 is formed by the aforementioned thin film of metalchromium (Cr), for example. A dielectric film 105 of the capacitor CP1is formed by the same insulator film, such as a silicon oxide film, forexample, as a gate electrode oxide film 102 of each of theaforementioned transistors NT1 and PT1, for example.

(Second Embodiment)

A voltage generation circuit according to a second embodiment of thepresent invention is now described with reference to FIG. 7. The voltagegeneration circuit according to the second embodiment is describedmainly with reference to a point different from the voltage generationcircuit according to the first embodiment shown in FIG. 1, and elementsof the second embodiment identical to those of the voltage generationcircuit shown in FIG. 1 are denoted by the same reference numerals, toomit redundant description.

The structural difference between the second embodiment and the firstembodiment resides in the following point: As shown in FIG. 7, aninverter INV1 is provided between a clock input terminal 1 and acapacitor CP1 in the voltage generation circuit according to thisembodiment. A clock signal CLK is applied to a common node between gateterminals G of an n-channel MOS transistor NT1 and a p-channel MOStransistor PT1 as such, and applied to the capacitor CP1 through theinverter INV1.

In place of the pair of clock signals CLK and /CLK inverted in phase toeach other shown in FIG. 1, therefore, the voltage generation circuitaccording to the second embodiment can receive only the single clocksignal CLK.

Further, a negative voltage VBB can be efficiently generated due to adelay effect through the inverter INV1 by applying the clock signal CLKin the aforementioned manner. A node ND1 can be set in a positivevoltage state while reducing a conducting state of the n-channel MOStransistor NT1 and the positive voltage can be inhibited frominfluencing the drain terminal D, set in a negative voltage state, ofthe n-channel MOS transistor NT1 at the time t1 shown in FIG. 2.

According to the voltage generation circuit of the second embodiment, ashereinabove described, the following effects can be attained in additionto the effects of the voltage generation circuit according to the firstembodiment:

(1) The voltage generation can receive only one clock signal CLK,whereby the structure of an external circuit generating the clock signalCLK can be simplified as compared with the case of employing the twoclock signals CLK and /CLK.

(2) The negative voltage can be efficiently generated due to the delayeffect through the inverter INV.

The aforementioned second embodiment can also be carried out in thefollowing mode: As shown in FIG. 8, the inverter INVI may be so providedas to apply the clock signal CLK to the common node between the gateterminals G of the n-channel MOS transistor NT1 and the p-channel MOStransistor PT1 through the inverter INV1.

(3) Third Embodiment

A voltage generation circuit according to a third embodiment of thepresent invention is now described with reference to FIGS. 9 to 15. Thevoltage generation circuit according to the third embodiment isdescribed mainly with reference to a point different from the voltagegeneration circuit according to the first embodiment shown in FIG. 1,and elements of the third embodiment identical to those of the voltagegeneration circuit shown in FIG. 1 are denoted by the same referencenumerals, to omit redundant description.

The structural difference between the third embodiment and the firstembodiment resides in the following point: According to this embodiment,a pair of voltage generation circuits shown in FIG. 1 are employed. Avoltage generation circuit capable of more efficiently performingpumping can be implemented due to this circuit structure. Thetheoretical value of the negative voltage VBB reaches the maximumtheoretical value (−VDD) and hence a voltage generation circuit capableof generating a large negative voltage can be implemented.

The voltage generation circuit shown in FIG. 9 has two capacitors(pumping capacitors) CP1 and CP2, and generates a prescribed negativevoltage VBB through nodes ND1 and ND2 connected to single terminals ofthe capacitors CP1 and CP2, respectively.

The voltage generation circuit comprises two pairs of transistors NT1,PT1, NT2 and PT2, and the n-channel MOS transistors NT1 and NT2 havesource terminals S connected to the nodes ND1 and ND2 respectively anddrain terminals D connected in common for defining a voltage outputterminal 3 outputting the negative potential VBB. The p-channel MOStransistors PT1 and PT2 have source terminals S connected to the nodesND1 and ND2, respectively, and drain terminals D defining groundterminals (reference potential terminals).

Gate terminals G of the n-channel MOS transistor NT1 and the p-channelMOS transistor PT1 are connected in common and connected to the nodeND2. Gate terminals G of the n-channel MOS transistor NT2 and thep-channel MOS transistor PT2 are connected in common and connected tothe node ND1.

Terminals of the capacitors CP1 and CP2 not connected to the nodes ND1and ND2 define clock input terminals 1 and 2, to which clock signals CLKand /CLK inverted in phase to each other are applied respectively.

The outline of operation of generating the negative voltage from thevoltage generation circuit having the aforementioned structure is nowdescribed with reference to FIG. 10.

When the clock signal CLK starts to go low (0 V) at a time t1 shown inFIG. 10, the potential VN1 of the node ND1 lowers to reach a negativevoltage (see (a) and (c) in FIG. 10), while the n-channel MOS transistorNT2 makes transition to an OFF state and the p-channel MOS transistorPT2 makes transition to an ON state in response thereto. At this time,there is no difference by the threshold voltage (Vthp2) between the nodeND2 and the ground voltage GND since the gate potential of the p-channelMOS transistor PT2 is a negative potential, and the charges in the nodeND2 are extracted to GND.

When the clock signal /CLK starts to go high (VDD), the potential VN2 ofthe node ND2 is pulled up by a level corresponding to the high level(VDD) of the clock signal /CLK (see (b) and (d) in FIG. 10) and rises,while the n-channel MOS transistor NT1 makes transition to an ON stateand the p-channel MOS transistor PT1 makes transition to an OFF state inresponse thereto.

At this time, the p-channel MOS transistor PT2 is turned on so thatcharges stored in the capacitor CP2 are extracted to the ground terminal(GND), followed by reduction of the potential VN2 of the node ND2 (see(d) in FIG. 10).

Due to the transition of the n-channel MOS transistor NT1 to the ONstate, further, charges proportional to the capacitance of the capacitorC1 flow from the drain terminal D of the n-channel MOS transistor NT1toward the node ND1. These charges are stored in the capacitor CP1because the p-channel MOS transistor PT1 is in an OFF state, and thepotential VN1 of the node ND1 rises in response thereto (see (c) in FIG.10).

Then, the clock signal CLK starts to go high and the clock signal /CLKstarts to go low at a time t2, whereby the pairs of transistors performoperation reverse to that at the aforementioned time t1.

When the clock signal CLK starts to go high H at the time t2, thepotential VN1 of the node ND1 is pulled up by a level corresponding tothe high level (VDD) of the clock signal CLK (see (a) and (c) in FIG.10) and rises, while the n-channel MOS transistor NT2 makes transitionto an ON state and the p-channel MOS transistor PT2 makes transition toan OFF state in response thereto.

When the clock signal /CLK starts to go low, the potential VN2 of thenode N2 lowers to a negative voltage (see (b) and (d) in FIG. 10) whilethe n-channel MOS transistor NT1 makes transition to an OFF state andthe p-channel MOS transistor PT1 makes transition to an ON state inresponse thereto. At this time, there is no difference by the thresholdvoltage (Vthp1) between the node ND1 and the ground voltage GND sincethe gate potential of the p-channel MOS transistor PT1 is a negativepotential, and the charges in the node ND1 are extracted to GND.

At this time, the p-channel MOS transistor PT1 is turned on so that thecharges stored in the capacitor CP1 are extracted to the ground terminal(GND), followed by reduction of the potential VN1 of the node ND1 (see(c) in FIG. 10).

Further, the n-channel MOS transistor NT2 is turned on so that chargesproportional to the capacitance of the capacitor CP2 flow from the drainterminal D of the n-channel MOS transistor NT2 toward the node ND2.These charges are stored in the capacitor CP2 since the p-channel MOStransistor PT2 is in an OFF state, and the potential VN2 of the node ND2rises in response thereto (see (d) in FIG. 10).

The clock signal CLK starts to go low again at a time t3, wherebyoperation similar to that at the aforementioned time t1 is performed.The aforementioned operation is so repeated as to pump the charges fromthe drain terminal D of either the n-channel MOS transistor NT1 or NT2every half cycle of the clock signal CLK or /CLK, for rendering thevoltage VBB of the drain terminal D negative (see (e) in FIG. 10).

According to the voltage generation circuit of this embodiment, pumpingcan be more efficiently performed by carrying out pumping operation forrendering the voltage negative every half cycle of the clock signal.Consequently, the speed for rendering the voltage negative can beincreased beyond that of the voltage generation circuit according to thefirst embodiment, as clearly understood when comparing (d) in FIG. 2with (e) in FIG. 10.

The outline of the sectional structure of the voltage generation circuitaccording to this embodiment formed on a semiconductor substrate is nowdescribed with reference to FIG. 11. FIG. 12 shows an equivalent circuitof this case.

As shown in FIG. 11, the voltage generation circuit according to thisembodiment is also formed on a P-type silicon substrate having a triplewell structure of a P-type well, N-type wells and another P-type well,similarly to the voltage generation circuit according to the firstembodiment.

The n-channel transistors NT1 and NT2 are formed on the P-type well asMOSFETs respectively, and each drain terminal D (the voltage outputterminal 3) is connected to the P-type well for obtaining back gatepotentials thereof.

The p-channel transistors PT1 and PT2 are formed on the N-type wells asMOSFETs, and the clock signals CLK and /CLK are applied to thecorresponding N-type wells respectively for obtaining back gatepotentials thereof.

The capacitor CP1 is separately formed on the N-type well as a p-channeltransistor having a source terminal and a drain terminal connected incommon and its gate terminal G is connected to the node ND1, while thecapacitor CP2 is separately formed on the other N-type well as ap-channel transistor having a source terminal and a drain terminalconnected in common and its gate terminal G is connected to the nodeND2.

FIGS. 13 to 15 show the differences between current drivingcharacteristics of the voltage generation circuit according to thisembodiment formed on the P-type silicon substrate having a triple wellstructure as described above and the conventional voltage generationcircuit (voltage generation circuit formed on a P-type silicon substratehaving a double well structure of a P-type well and an N-type well andusing a p-channel MOS transistor as a driving transistor) shown in FIG.42. Referring to FIGS. 13 to 15, “IBBp” denotes a driving current by theaforementioned conventional voltage generation circuit, and “IBBn”denotes a driving current by the voltage generation circuit according tothis embodiment.

FIG. 13 shows the results of simulation of the values of the drivingcurrents flowing from the voltage output terminals 3 and 30 to theground terminals (GND) when setting the sizes of the driving transistorsidentical while varying the capacitance of the capacitors. In thissimulation, a power supply voltage of 3.3 V, a rule of 0.35 μm, the roomtemperature and the like are employed as parameters.

It is understood from FIG. 13 that the driving current of the n-channelMOS transistor exceeds that of the p-channel MOS transistor when thecapacitance of the capacitor is increased. This indicates that thisembodiment employing the n-channel MOS transistor as the drivingtransistor is more advantageous for obtaining a large driving current,and can reduce the size of the driving transistor for obtaining the samedriving current.

FIG. 14 shows results of simulation of values of driving currents whensetting the transistor sizes and the aforementioned parameters identicalwhile varying the initial voltage values (VBB) of the voltage outputterminals 3 and 30.

It is understood from FIG. 14 that the drivability of the p-channel MOStransistor is reduced as compared with the n-channel MOS transistor asthe voltage VBB of the voltage output terminal is rendered negative.This indicates superiority of the drivability of the n-channel MOStransistor at the prescribed negative voltage VBB.

FIG. 15 shows results of simulation of values of the driving currentswhen setting the transistor sizes identical while varying power supplyvoltages. Referring to FIG. 15, a rule of 0.18 μm is employed as aparameter.

It is understood from FIG. 15 that the drivability of the n-channel MOStransistor is superior to that of the p-channel MOS transistor also whenthe power supply voltage is set to a low level. This indicatessuperiority of the drivability of the n-channel MOS transistor in thecase of setting the power supply voltage to a low level.

According to the voltage generation circuit of the third embodiment, ashereinabove described, the following effects can be attained in additionto the effects of the voltage generation circuit according to theaforementioned first embodiment: In the voltage generation circuitaccording to this embodiment, the pumping operation for rendering thevoltage negative is performed every half cycle of the clock signal sothat pumping can be more efficiently performed. Consequently, the speedfor rendering the voltage negative can be increased in the voltagegeneration circuit.

The aforementioned third embodiment can also be carried out in thefollowing modes:

(1) While the clock signals CLK and /CLK are applied to the N-type wellsformed with the p-channel MOS transistors PT1 and PT2 for obtaining theback gate potentials thereof in the aforementioned third embodiment, thepresent invention is not restricted to this. Alternatively, a positivepotential such as a power supply voltage VDD, for example, may beapplied to the N-type wells as shown in FIG. 16, in order to obtain theback gate potentials of the transistors PT1 and PT2. FIG. 17 shows anequivalent circuit of this case.

(2) While the capacitors CP1 and CP2 are formed by the p-channeltransistors separately formed on the N-type wells in the aforementionedthird embodiment, the present invention is not restricted to this.Alternatively, the capacitors CP1 and CP2 may be formed by n-channeltransistors separately formed on P-type wells as shown in FIG. 18, forexample. FIG. 19 shows an equivalent circuit of this case.

(3) While the voltage generation circuit is formed on the P-type siliconsubstrate having a triple well structure in the aforementioned thirdembodiment, the present invention is not particularly restricted tothis. Alternatively, the voltage generation circuit may be formed on anN-type silicon substrate having a double well structure of an N-typewell and P-type wells as shown in FIG. 20, for example.

(4) The aforementioned voltage generation circuit may alternatively beformed on an insulator film formed on a silicon substrate, as shown inFIG. 21. In this case, each active layer (source/drain region) of then-channel MOS transistors NT1 and NT2 and the p-channel MOS transistorsPT1 and PT2 is formed from a semiconductor layer of single-crystallinesilicon, polycrystalline silicon or amorphous silicon located in aninterlayer isolation film 101 formed on the aforementioned insulatorfilm.

The capacitors CP1 and CP2 are also formed on the insulator film formedon the aforementioned silicon substrate, and at least single electrodes(lower electrodes 103 in FIG. 21) thereof are formed by n-type regionsor p-type regions (n-type regions in FIG. 21) formed on parts of theaforementioned semiconductor layer. Further, dielectric films 105 of thecapacitors CP1 and CP2 are formed by the same insulating films, such assilicon oxide films, for example, as gate electrode oxide films 102 ofthe aforementioned transistor NT1, PT1, NT2 and PT2, for example.

(5) The aforementioned voltage generation circuit may be formed on aglass substrate, as shown in FIG. 22. In this case, each active layer(source/drain region) of the n-channel MOS transistors NT1 and NT2 andthe p-channel MOS transistors PT1 and PT2 is formed from a semiconductorlayer of polycrystalline silicon or amorphous silicon located in aninterlayer isolation film 101 formed on the aforementioned glasssubstrate, similarly to FIG. 6. Further, each gate electrode G of thetransistors NT1, NT2, PT1 and PT2 is formed by a thin film of metalchromium (Cr), for example. Alternatively, the gate electrode G may beformed by a silicide thin film or the like.

The capacitors CP1 and CP2 are also formed on the aforementioned glasssubstrate, and at least single electrodes (lower electrodes 103 in FIG.22) thereof are formed by n-type regions or p-type regions (n-typeregions in FIG. 22) formed in parts of the aforementioned semiconductorlayer, and upper electrodes 104 are formed by the aforementioned thinfilm of metal chromium (Cr). Further, dielectric films 105 of thecapacitors CP1 and CP2 are formed by the same insulator films, e.g.,silicon oxide films, as gate electrode oxide films 102 of thetransistors NT1, NT2, PT1 and PT2, for example.

FIGS. 23 and 24 show the differences between the current drivingcharacteristics of the voltage generation circuit according to thisembodiment formed on the glass substrate as described above and theconventional voltage generation circuit shown in FIG. 42. Referring toFIGS. 23 and 24, “IBBp” denotes a driving current by the aforementionedconventional voltage generation circuit, and “IBBn” denotes a drivingcurrent by the voltage generation circuit according to this embodiment.In this case, the transistors are formed on the glass substrate aspolycrystalline silicon thin film transistors.

FIG. 23 shows the results of simulation of the values of the drivingcurrents flowing from the voltage output terminals 3 and 30 to theground terminals (GND) when setting capacitance of the capacitorsidentical while varying the sizes of the driving transistors. In thissimulation, a power supply voltage of 12 V, a rule of 5 μm, the roomtemperature and the like are employed as parameters.

It is understood from FIG. 23 that the n-channel MOS transistorsemployed as driving transistors are superior in current drivability andlayout area for obtaining the same driving current to the p-channel MOStransistors.

FIG. 24 shows results of simulation of values of driving currents whensetting the transistor sizes and the aforementioned parameters identicalwhile varying the initial voltage values (VBB) of the voltage outputterminals 3 and 30, similarly to FIG. 14.

It is understood from FIG. 24 that the drivability of the p-channel MOStransistors is reduced as compared with the n-channel MOS transistors asthe voltage VBB of the voltage output terminal is rendered negative alsowhen the voltage generation circuit is formed on the glass substrate.This indicates the superiority of the drivability of the n-channel MOStransistors at the prescribed negative voltage VBB.

(6) The voltage generation circuit may be formed on a glass substrateand the n-channel MOS transistors NT1 and NT2 and the p-channel MOStransistors PT1 and PT2 may be formed by not the top gate transistorsshown in FIG. 22 but by bottom gate transistors, as shown in FIG. 25.

(7) While the pair of clock signals CLK and /CLK applied to the voltagegeneration circuit are inverted in phase to each other as shown at (a)and (b) in FIG. 10, the present invention is not restricted to this. Forexample, a pair of clock signals PCLK1 and PCLK2 shown in FIG. 26 may beseparately formed and input in the clock input terminals 1 and 2respectively.

The pair of clock signals PCLK1 and PCLK2 are formed to have periods τ1and τ2 when both of the clock signals PCLK1 and PCLK2 go low in logic inphase inversion from high logical levels to low logical levels, as shownin FIG. 26.

Thus, due to the periods τ1 and τ2 when both of the clock signals PCLK1and PCLK2 go low, the aforementioned nodes ND1 and ND2 can be set topositive voltages after reliably turning off the driving transistors orthe like, for example. Therefore, the negative voltage can beefficiently generated. The clock signals PCLK1 and PCLK2 may beindividually formed or may be formed from a single clock signal source.

FIG. 27 shows an example of forming the clock signals PCLK1 and PCLK2from a single clock signal source. In this case, a clock signal CLK isapplied to a logic circuit 5 for forming the clock signals PCLK1 andPCLK2 inverted in phase to each other and a delay circuit 4 adjusting aperiod so that the two clock signals PCLK1 and PCLK2 have theaforementioned periods τ1 and τ2 when both of the clock signals PCLK1and PCLK2 go low through an inverter circuit INV1, for readily andautomatically producing the clock signals PCLK1 and PCLK2 shown in FIG.26.

(Fourth Embodiment)

A voltage generation circuit according to a fourth embodiment of thepresent invention is now described with reference to FIGS. 28 to 31. Thevoltage generation circuit according to the fourth embodiment isdescribed mainly with reference to a point different from the voltagegeneration circuit according to the first embodiment shown in FIG. 1,and elements of the fourth embodiment identical to those of the voltagegeneration circuit shown in FIG. 1 are denoted by the same referencenumerals, to omit redundant description.

The structural difference between the fourth embodiment and the firstembodiment resides in the following point: In the voltage generationcircuit according to this embodiment, the p-channel transistor shown inFIG. 1 is changed to an n-channel MOS transistor. More specifically, thep-channel MOS transistor PT1 shown in FIG. 1 is replaced with ann-channel MOS transistor NT2, as shown in FIG. 28.

The voltage generation circuit shown in FIG. 28 comprises a capacitorCP1, a first n-channel MOS transistor NT1, the second n-channel MOStransistor NT2 and the like.

The first n-channel MOS transistor (driving transistor) NT1 has a sourceterminal S connected to a node ND1, a drain terminal D defining avoltage output terminal 3 outputting a negative voltage VBB and a gateterminal G connected to a clock input terminal 2. The second n-channelMOS transistor NT2 has a drain terminal D and a gate terminal Gconnected to the node ND1 and a source terminal S defining a groundterminal (reference potential terminal).

The capacitor CP1 has a first electrode connected to the node ND1 and asecond electrode connected to a clock input terminal 1. Clock signalsCLK and /CLK inverted in phase to each other are applied to the clockinput terminals 1 and 2 respectively. The capacitor CP1 may be formed byan n-channel MOS transistor or a p-channel MOS transistor having asource terminal and a drain terminal connected in common.

The outline of operation of generating the negative voltage from thevoltage generation circuit having the aforementioned structure is nowdescribed with reference to FIG. 29. The clock signals CLK and /CLKshown at (a) and (b) in FIG. 29 are merely inverted in phase to eachother.

When the clock signal CLK starts to go low (0 V) at a time t1 shown inFIG. 29, the potential VN1 of the node ND1 lowers to reach a negativevoltage (see (a) and (c) in FIG. 29). When the clock signal /CLK goeshigh (VDD), the first n-channel MOS transistor NT1 is turned on, andcharges proportional to the capacitance of the capacitor C1 flow fromthe drain terminal D of the n-channel MOS transistor NT1 toward the nodeND1. These charges are stored in the capacitor CP1 since the secondn-channel MOS transistor NT2 is in an OFF state, and the potential VN1of the node ND1 rises in response thereto (see (c) in FIG. 29).

When the clock signal CLK starts to go high at a time t2, the potentialVN1 of the node ND1 is pulled up by a level corresponding to the highlevel (VDD) of the clock signal CLK and further rises. When the clocksignal CLK goes high, the second n-channel MOS transistor NT2 is turnedon. Therefore, the charges stored in the capacitor CP1 are extracted tothe ground terminal (GND), followed by reduction of the potential VN1 ofthe node ND1 (see (c) in FIG. 29).

When the clock signal CLK starts to go low again at a time t3, operationsimilar to that at the aforementioned time t1 is performed. Theaforementioned operation is so repeated as to pump the charges from thedrain terminal D of the first n-channel MOS transistor NT1 to the groundterminal every cycle of the clock signals CLK and /CLK, for renderingthe voltage VBB of the drain terminal D of the first n-channel MOStransistor NT1 negative (see (d) in FIG. 29).

Also when the output negative voltage VBB lowers in the voltagegeneration circuit according to this embodiment, the potentialdifference between the source terminal S and the gate terminal G forturning on the first n-channel MOS transistor NT1 is supplied by theclock signal /CLK and hence drivability of the first n-channel MOStransistor NT1 can be sufficiently guaranteed regardless of the value ofthe output negative voltage VBB, similarly to the voltage generationcircuit according to the first embodiment.

Further, the n-channel transistor is employed as the driving transistor,whereby the operating speed can be increased as compared with the caseof employing the p-channel transistor as the driving transistor due toits characteristics, and the drivability can be improved. When securingability equivalent to that of the p-channel transistor with then-channel transistor, the element areas of the transistors can bereduced.

The outline of the sectional structure of the voltage generation circuitaccording to this embodiment formed on a semiconductor substrate is nowdescribed with reference to FIG. 30. FIG. 31 shows an equivalent circuitof this case.

As shown in FIG. 30, the voltage generation circuit is formed on aP-type silicon substrate having a triple well structure formed by P-typewells, an N-type well and a P-type well.

The first n-channel MOS transistor NT1 is formed on the P-type well as aMOSFET, and the drain terminal D (the voltage output terminal 3) isconnected to this P-type well for obtaining its back gate potential.

The second n-channel MOS transistor NT2 is formed on the P-type well asa MOSFET, and the node ND1 is connected to this P-type well forobtaining its back gate potential.

The capacitor CP1 is separately formed on the P-type well as ann-channel MOSFET having a source terminal and a drain terminal connectedin common, and its gate terminal G is connected to the node ND1.

The voltage generation circuit according to this embodiment can alsogenerate the negative voltage equivalent to that of the voltagegeneration circuit according to the first embodiment for attainingsimilar effects due to the aforementioned structure.

The aforementioned fourth embodiment can also be carried out in thefollowing modes:

(1) While the voltage generation circuit is formed on the P-type siliconsubstrate having a triple well structure, the present invention is notparticularly restricted to this. For example, the aforementioned voltagegeneration circuit may be formed on an N-type silicon substrate having adouble well structure of an N-type well and P-type wells, as shown inFIG. 32.

(2) The aforementioned voltage generation circuit may be formed on aglass substrate, as shown in FIG. 33. In this case, each active layer(source/drain region) of the first and second n-channel MOS transistorsNT1 and NT2 is formed from a semiconductor layer of polycrystallinesilicon or amorphous silicon located in an interlayer isolation film 101formed on the glass substrate. Further, each gate electrode G of thetransistors NT1 and NT2 is formed by a thin film of metal chromium (Cr),for example. Alternatively, the gate electrode G may be formed by asilicide thin film.

The capacitor CP1 is also formed on the aforementioned glass substrate,and at least one electrode (a lower electrode 103 in FIG. 33) is formedby an n-type region formed on part of the aforementioned semiconductorlayer, and its upper electrode 104 is formed by the aforementioned thinfilm of metal chromium (Cr), for example. A dielectric film 105 of thecapacitor CP1 is formed by the same insulator film, such as a siliconoxide film, for example, as each gate electrode oxide film 102 of theaforementioned transistors NT1 and NT2.

(3) The voltage generation circuit may be formed on an insulator filmformed on a silicon substrate, similarly to FIG. 21.

(4) The clock signals PCLK1 and PCLK2 having the periods τ1 and τ2 whenboth of the clock signals PCLK1 and PCLK2 go low in logic in phaseinversion may be employed as the clock signals CLK and /CLK, as shown inFIG. 26.

(Fifth Embodiment)

A voltage generation circuit according to a fifth embodiment of thepresent invention is now described with reference to FIGS. 34 to 37. Thevoltage generation circuit according to the fifth embodiment isdescribed mainly with reference to a point different from the voltagegeneration circuit according to the third embodiment shown in FIG. 9,and elements of the fifth embodiment identical to those of the voltagegeneration circuit shown in FIG. 9 are denoted by the same referencenumerals, to omit redundant description.

The structural difference between the fifth embodiment and the thirdembodiment resides in the following point: As shown in FIG. 34, thep-channel MOS transistors in the third embodiment are replaced withn-channel MOS transistors in the voltage generation circuit according tothis embodiment. More specifically, the p-channel MOS transistors PT1and PT2 shown in FIG. 9 are replaced with n-channel MOS transistors NT2and NT2′ shown in FIG. 34.

The voltage generation circuit shown in FIG. 34 comprises two pairs oftransistors NT1, NT2, NT1′ and NT2′, while the first n-channel MOStransistors NT1 and NT1′ have source terminals S connected to nodes ND1and ND2 respectively and drain terminals D connected in common fordefining a voltage output terminal 3 outputting a negative voltage VBB.The second n-channel MOS transistors NT2 and NT2′ have drain terminals Dconnected to the nodes ND1 and ND2 respectively and source terminals Sdefining ground terminals (reference potential terminals).

Gate terminals G of the first and second n-channel MOS transistors NT1and NT2′ are connected to the node ND2, while gate terminals G of thefirst and second n-channel MOS transistors NT1′ and NT2 are connected tothe node ND1.

The outline of operation of generating the negative voltage from thevoltage generation circuit having the aforementioned structure is nowdescribed with reference to FIG. 35.

When a clock signal CLK starts to go low (0 V) at a time t1 shown inFIG. 35, the potential VN1 of the node ND1 lowers to reach a negativevoltage (see (a) and (c) in FIG. 35), while the first n-channel MOStransistor NT1′ makes transition to an OFF state and the secondn-channel MOS transistor NT2′ makes transition to an ON state inresponse thereto.

When a clock signal /CLK starts to go high (VDD), the potential VN2 ofthe node ND2 is pulled up by a level corresponding to the high level(VDD) of the clock signal /CLK (see (b) and (d) in FIG. 35) and rises,while the first n-channel MOS transistor NT1 makes transition to an ONstate and the second n-channel MOS transistor NT2 makes transition to anOFF state in response thereto.

At this time, the second n-channel MOS transistor NT2′ is turned on,whereby charges stored in the capacitor CP2 are extracted to the groundterminal (GND), and the potential VN2 of the node ND2 lowers in responsethereto (see (d) in FIG. 35).

Due to the transition of the first n-channel MOS transistor NT1 to theON state, charges proportional to the capacitance of the capacitor C1flow from the drain terminal D of the first n-channel MOS transistor NT1toward the node ND1. These charges are stored in the capacitor CP1 sincethe second n-channel MOS transistor NT2 is in an OFF state, and thepotential VN1 of the node ND1 rises in response thereto (see (c) in FIG.35).

Then, the clock signal CLK starts to go high and the clock signal /CLKstarts to go low at a time t2, whereby the pairs of transistors performoperation reverse to that at the aforementioned time t1.

When the clock signal CLK starts to go high H at the time t2, thepotential VN1 of the node ND1 is pulled up by a level corresponding tothe high level (VDD) of the clock signal CLK and rises (see (a) and (c)in FIG. 35), while the first n-channel MOS transistor NT1′ makestransition to an ON state and the second n-channel MOS transistor NT2′makes transition to an OFF state in response thereto.

When the clock signal /CLK starts to go low, the potential VN2 of thenode N2 lowers to a negative voltage (see (b) and (d) in FIG. 35) whilethe first n-channel MOS transistor NT1 makes transition to an OFF stateand the second n-channel MOS transistor NT2 makes transition to an ONstate in response thereto.

At this time, the second n-channel MOS transistor NT2 is turned on,whereby the charges stored in the capacitor CP1 are extracted to theground terminal (GND), followed by reduction of the potential VN1 of thenode ND1 (see (c) in FIG. 35).

Further, the first n-channel MOS transistor NT1′ is turned on, wherebycharges proportional to the capacitance of the capacitor CP2 flow fromthe drain terminal D of the first n-channel MOS transistor NT1′ towardthe node ND2. These charges are stored in the capacitor CP2 since thesecond n-channel MOS transistor NT2′ is in the OFF state, and thepotential VN2 of the node ND2 rises in response thereto (see (d) in FIG.35).

When the clock signal CLK starts to go low again at a time t3, operationsimilar to that at the aforementioned time t1 is performed. Theaforementioned operation is so repeated as to pump the charges from thedrain terminal D of either the first n-channel MOS transistor NT1 orNT1′ every half cycle of the clock signal CLK or /CLK, for rendering thevoltage VBB of the drain terminal D negative (see (e) in FIG. 35).

Also according to the voltage generation circuit of this embodiment,pumping can be more efficiently performed by carrying out pumpingoperation for rendering the voltage negative every half cycle of theclock signal, and the speed for rendering the voltage negative can beincreased similarly to the voltage generation circuit according to thethird embodiment.

The outline of the sectional structure of the voltage generation circuitaccording to this embodiment formed on a semiconductor substrate is nowdescribed with reference to FIG. 36. FIG. 37 shows an equivalent circuitof this case.

As shown in FIG. 36, the voltage generation circuit according to thisembodiment is also formed on a P-type silicon substrate having a triplewell structure of P-type wells, an N-type well and a P-type well,similarly to the voltage generation circuit according to the thirdembodiment.

Each of the first n-channel transistors NT1 and NT1′ is formed on theP-type well as MOSFETs respectively, and the drain terminal D (thevoltage output terminal 3) thereof is connected to the P-type well forobtaining back its gate potential.

The second n-channel transistor NT2 is formed on the P-type well as aMOSFET and the node ND1 is connected to this P-type well for obtainingits back gate potential, while the second n-channel transistor NT2′ isformed on the P-type well as a MOSFET and the node ND2 is connected tothis P-type well for obtaining its back gate potential.

The capacitor CP1 is separately formed on the P-type well as ann-channel transistor having a source terminal and a drain terminalconnected in common and its gate terminal G is connected to the nodeND1, while the capacitor CP2 is separately formed on the P-type well asan n-channel transistor having a source terminal and a drain terminalconnected in common and its gate terminal G is connected to the nodeND2.

The voltage generation circuit shown in FIG. 36 can also generate anegative voltage equivalent to that of the voltage generation circuitaccording to the third embodiment and attain similar effects due to theaforementioned structure.

The aforementioned fifth embodiment can also be carried out in thefollowing modes:

(1) While the voltage generation circuit according to the aforementionedfifth embodiment is formed on the P-type silicon substrate having atriple well structure, the present invention is not particularlyrestricted to this. For example, the voltage generation circuit may beformed on an N-type silicon substrate having a double well structure ofan N-type well and P-type wells, as shown in FIG. 38.

In this case, each of the first and second n-channel MOS transistorsNT1, NT2, NT1′ and NT2′ is formed on the N-type silicon substrate as asilicon transistor of single-crystalline silicon, polycrystallinesilicon or amorphous silicon. Each of the capacitors CP1 and CP2 isformed by a silicon electrode and an insulator thin film formed on theN-type silicon substrate.

(2) The voltage generation circuit may be formed on a glass substrate,as shown in FIG. 39. In this case, each active layer (source/drainregion) of the first and second n-channel MOS transistors NT1, NT2, NT1′and NT2′ is formed from a semiconductor layer of polycrystalline siliconor amorphous silicon located in an interlayer isolation film 101 formedon the glass substrate, similarly to FIG. 33. Further, each gateelectrode G of the transistors NT1, NT2, NT1′ and NT2′ is formed by athin film of metal chromium (Cr), for example. The gate electrode G mayalternatively be formed by a silicide thin film or the like.

The capacitors CP1 and CP2 are also formed on the aforementioned glasssubstrate, and at least single electrodes (lower electrodes 103 in FIG.39) are formed by n-type regions formed on parts of the aforementionedsemiconductor layer, and upper electrodes 104 are formed by theaforementioned thin film of metal chromium (Cr), for example. Further,dielectric films 105 of the capacitors CP1 and CP2 are formed by thesame insulator films, such as silicon oxide films, for example, as gateelectrode oxide films 102 of the aforementioned transistors NT1, NT2,NT1′ and NT2′, for example. The aforementioned transistors NT1, NT2,NT1′ and NT2′ may be formed not by the top gate transistors shown inFIG. 39 but by bottom gate transistors.

(3) The voltage generation circuit may be formed on an insulator filmformed on a silicon substrate, similarly to that shown in FIG. 21.

(4) Clock signals PCLK1 and PCLK2 having periods τ1 and τ2 when both ofthe clock signals PCLK1 and PCLK2 go low in phase inversion may beemployed as the clock signals CLK and /CLK, similarly to those shown inFIG. 26.

(Embodiment of Display Unit)

A display unit comprising the voltage generation circuit according tothe present invention is now described with reference to FIG. 40.Referring to FIG. 40, the present invention is applied to a polysiliconTFT liquid crystal display unit as the display unit comprising thevoltage generation circuit.

The display unit shown in FIG. 40 comprises a display part 50, a scanline driving circuit 60, a data driving circuit 70, a voltage generationcircuit 80, a level conversion circuit 90 etc. formed on a glasssubstrate.

The display part 50 includes a plurality of display pixels PX arrangedon intersections between a plurality of scan lines Y1 to Yn and aplurality of data lines X1 to Xm in the form of a matrix, activeswitching elements ST provided for the respective display pixels PX forcontrolling an applied voltage to the display pixels PX, and the like.The active switching elements ST are formed by polysilicon thin-filmtransistors, for example.

The scan line driving circuit 60 scans the plurality of scan lines Y1 toYn, and applies a driving voltage for activating the active switchingelements ST to the scan lines Y1 to Yn. The data driving circuit 70outputs pixel information corresponding to the scan lines Y1 to Yn tothe data lines X1 to Xm.

In this embodiment, the voltage generation circuit 80 has a circuitstructure such as that shown in FIG. 9 and a sectional structure such asthat shown in FIG. 22, for example, and is formed on the glasssubstrate. In other words, the voltage generation circuit 80, employinga pair of voltage generation circuits shown in FIG. 1, has twocapacitors and generates a prescribed negative voltage through nodesconnected to single terminals of the capacitors. Therefore, the voltagegeneration circuit 80 can efficiently perform pumping every half cycleof clock signals HCLK1 and HCLK2 (or CLK and /CLK). Respective n-channeltransistors and respective p-channel transistors forming the voltagegeneration circuit 80 are formed on the glass substrate as polysiliconthin-film transistors.

The level conversion circuit 90 steps up/converts the levels of signalsapplied to the voltage generation circuit 80 as the clock signals HCLK1and HCLK2. According to this embodiment, the level conversion circuit 90level-converts clock signals LCLK1 and LCLK2 of 0 to 5 V to the clocksignals HCLK1 and HCLK2 of 0 to 15 V, and applies the converted clocksignals HCLK1 and HCLK2 to the voltage generation circuit 80, forexample. Thus, the voltage generation circuit 80 can readily andefficiently generate a prescribed negative voltage VBB required in thescan line driving circuit 60 due to the level conversion of the clocksignals.

Due to the aforementioned structure, the display unit comprising thevoltage generation circuit according to this embodiment can attain thefollowing effects:

(1) While a voltage from a ground potential to a power supply voltageVDD is generally applied to the scan lines Y1 to Yn, power consumptionof the liquid crystal display unit can be reduced and off margins of theactive switching elements ST can be increased by applying a voltage fromthe prescribed negative voltage to half the power supply voltage VDD dueto the voltage generation circuit 80 loaded on the liquid crystaldisplay unit.

(2) While AC-driving liquid crystal electrodes opposed to each other forreducing power consumption, by loading the voltage generation circuit 80on the liquid crystal display unit, the gate potential of pixeltransistors can be set to a lower negative potential due to the largeachieved negative voltage regardless of the threshold voltage oftransistors, data leak can be prevented and power consumption can bereduced.

(3) While an external capacitor is provided outside the liquid crystaldisplay unit as an element for storing a negative voltage as shown inFIG. 40 when the negative voltage is supplied to the liquid crystaldisplay unit, the capacitance of the external capacitor can be reducedand the external capacitor may be miniaturized or omitted by loading thevoltage generation circuit 80 on the liquid crystal display unit.

(4) While the liquid crystal display unit must reach the negativevoltage VBB as soon as possible upon power supply, the negative voltageVBB can be quickly supplied due to efficient pumping of the voltagegeneration circuit 80.

(5) The display quality of the liquid crystal display unit can beimproved by loading the voltage generation circuit 80 having a largedriving current (drivability) thereon.

This embodiment can also be carried out in the following modes:

(1) The voltage generation circuit loaded on the liquid crystal displayunit is not particularly restricted to the voltage generation circuit 80having the circuit structure such as that shown in FIG. 9 and thesectional structure such as that shown in FIG. 22 and formed on theglass substrate.

For example, a voltage generation circuit having a circuit structuresuch as that shown in FIG. 1 and a sectional structure such as thatshown in FIG. 6 and formed on a glass substrate may be employed, or avoltage generation circuit having a circuit structure such as that shownin FIG. 9 and a sectional structure such as that shown in FIG. 25 andformed on a glass substrate may be employed.

Further, a voltage generation circuit having a circuit structure such asthat shown in FIG. 28 and a sectional structure such as that shown inFIG. 33 may be employed, or a voltage generation circuit having acircuit structure such as that shown in FIG. 34 and a sectionalstructure such as that shown in FIG. 39 and formed on a glass substratemay be employed.

(2) The liquid crystal display unit comprising the voltage generationcircuit according to the present invention is not particularlyrestricted to the aforementioned polysilicon TFT liquid crystal displayunit but the present invention is also similarly applicable to anamorphous silicon TFT liquid crystal display unit or the like, forexample.

(3) The display unit comprising the voltage generation circuit accordingto the present invention is not particularly restricted to theaforementioned liquid crystal display unit but the present invention isalso similarly applicable to another display unit such as an organic EL(electroluminescence) display unit, for example.

(4) The clock signals PCLK1 and PCLK2 having the periods τ1 and τ2 whenboth of the clock signals PCLK1 and PCLK2 go low in logic in phaseinversion as shown in FIG. 26 may be employed as the clock signals LCLK1and LCLK2.

In addition, changeable elements common to the aforementionedembodiments are as follows: While the voltage generation circuitgenerates the negative voltage VBB from the voltage output terminal 3with the reference potential of the ground potential (GND) in each ofthe aforementioned embodiments, the present invention is notparticularly restricted to this. The present invention is alsoapplicable to a case of setting the aforementioned reference potentialto a prescribed negative voltage and generating a negative voltage lowerthan the prescribed negative voltage from the voltage output terminal ofthe voltage generation circuit, or a case of setting the referencepotential to a prescribed positive voltage and generating a positivevoltage or a negative voltage lower than the prescribed positive voltagefrom the voltage output terminal of the voltage generation circuit.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims

What is claimed is:
 1. A voltage generation circuit having a capacitorand generating a prescribed voltage through a node connected to a firstterminal of said capacitor, comprising: an n-channel transistor havingone of a source terminal and a drain terminal connected to said nodewith the other one of said source terminal and said drain terminaldefining an output terminal outputting said prescribed voltage; and ap-channel transistor having one of a source terminal and a drainterminal connected to said node with the other one of said sourceterminal and said drain terminal defining a reference potentialterminal, wherein gate terminals of said n-channel transistor and saidp-channel transistor are connected in common, wherein one of two clocksignals inverted in phase to each other is applied to a second terminalof said capacitor while the other one of said two clock signals isapplied to said gate terminals connected in common without going througha capacitor, and wherein said voltage generation circuit is formed on aP-type semiconductor substrate having a triple well structure, saidn-channel transistor includes a MOSFET formed on a P-type well to whichsaid output terminal is connected for obtaining its back gate potential,said p-channel transistor includes a MOSFET formed on an N-type well towhich a positive potential is applied for obtaining its back gatepotential, and said capacitor includes an n-channel transistorseparately formed on a P-type well with a source terminal and a drainterminal connected in common and a gate terminal connected to said node.2. A voltage generation circuit having a capacitor and generating aprescribed voltage through a node connected to a first terminal of saidcapacitor, comprising: an n-channel transistor having one of a sourceterminal and a drain terminal connected to said node with the other oneof said source terminal and said drain terminal defining an outputterminal outputting said prescribed voltage; and a p-channel transistorhaving one of a source terminal and a drain terminal connected to saidnode with the other one of said source terminal and said drain terminaldefining a reference potential terminal, wherein gate terminals of saidn-channel transistor and said p-channel transistor are connected incommon, wherein one of two clock signals invented in phase to each otheris applied to a second terminal of said capacitor while the other one ofsaid two clock signals is applied to said gate terminals connected incommon without going through a capacitor, and wherein said voltagegeneration circuit is formed on an N-type semiconductor substrate havinga double well structure, said n-channel transistor includes a MOSFETformed on a P-type well to which said output terminal is connected forobtaining its back gate potential, said p-channel transistor includes aMOSFET formed on an N-type well to which a positive potential is appliedfor obtaining its back gate potential, and said capacitor includes ann-channel transistor separately formed on a P-type well with a sourceterminal and a drain terminal connected in common and a gate terminalconnected to said node.
 3. A voltage generation circuit having acapacitor and generating a prescribed voltage through a node connectedto a first terminal of said capacitor, comprising: an n-channeltransistor having one of a source terminal and a drain terminalconnected to said node with the other one of said source terminal andsaid drain terminal defining an output terminal outputting saidprescribed voltage; and a p-channel transistor having one of a sourceterminal and a drain terminal connected to said node with the other oneof said source terminal and said drain terminal defining a referencepotential terminal, wherein gate terminals of said n-channel transistorand said p-channel transistor are connected in common, wherein one oftwo clock signals inverted in phase to each other is applied to a secondterminal of said capacitor while the other one of said two clock signalsis applied to said gate terminals connected in common without goingthrough a capacitor, and wherein said voltage generation circuit isformed on a glass substrate, an active layer of each of said n-channeltransistor and said p-channel transistor is formed from a semiconductorlayer formed on said glass substrate, and at least one electrode of saidcapacitor is formed from an n-type region or a p-type region formed onpart of said semiconductor layer.
 4. The voltage generation circuitaccording to any one of claim 1, 2, or 3, further comprising an invertercircuit for forming said two clock signals on the basis of a singleclock signal.
 5. The voltage generation circuit according to any one ofclaim 1, 2, or 3, wherein said two clock signals have a period when bothof said two clock signals go low in logic in phase inversion.
 6. Thevoltage generation circuit according to any one of claim 1, 2, or 3,further comprising: a logic circuit for forming said two clock signalson the basis of a single clock signal, and a delay circuit adjusting aperiod so that said two clock signals have a period when both of saidtwo clock signals go low in logic in phase inversion.
 7. A display unitcomprising: a plurality of display pixels arranged on intersectionsbetween a plurality of scan lines and a plurality of data lines in theform of a matrix; a plurality of active switching elements provided forrespective said display pixels for controlling a voltage applied to saiddisplay pixels; a scan line driving circuit scanning said plurality ofscan lines while applying a driving voltage for activating saidplurality of active switching elements; and a voltage generation circuitoutputting a prescribed voltage to said scan line driving circuit,wherein said voltage generation circuit has a capacitor and generatessaid prescribed voltage trough a node connected to a first terminal ofsaid capacitor, said voltage generation circuit further including: ann-channel transistor having one of a source terminal and a drainterminal connected to said node with the other one of said sourceterminal and said drain terminal defining an output terminal outputtingsaid prescribed voltage, a p-channel transistor having one of a sourceterminal and a drain terminal connected to said node with the other oneof said source terminal and said drain terminal defining a referencepotential terminal, gate terminals of said n-channel transistor and saidchannel transistor are connected in common, and one of two clock signalsinverted in phase to each other is applied to a second terminal of saidcapacitor and the other one of said two clock signals is applied to saidgate terminals connected in common without going through a capacitor,wherein said voltage generation circuit is formed on a glass substrate,an active layer of each of said n-channel transistor and said p-channeltransistor is formed from a semiconductor layer formed on said glasssubstrate, and at least one electrode of said capacitor is formed froman n-type region or a p-type region formed on part of said semiconductorlayer.
 8. The display unit according to claim 7, further comprising alevel conversion circuit stepping up/converting the levels of signalsapplied to said voltage generation circuit as said clock signals.